View IMC008FLSP_6542643.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

e december 1997 order number: 290491-007 n single power supply n automatically reconfigures for 3.3 v and 5 v systems n 150 ns maximum access time with 5 v power supply n 250 ns maximum access time with 3.3 v power supply n high-performance random writes ? 0.85 mb/s sustained throughput ? 1 kb burst write at 10 mb/s n 25 a typical deep power-down n revolutionary architecture ? pipelined command execution ? write during erase ? series 2 command super-set n state-of-the-art 0.6 m etox? iv flash technology n 1 million erase cycles per block n up to 640 independent lockable blocks n pcmcia 2.1/jeida 4.1-compatible n pcmcia type 1 form factor n series 2+ users manual intels series 2+ flash memory card sets the new record for high-performance disk emulation and execute- in-place (xip) applications in mobile pcs and dedicated equipment. manufactured with intels 28f016sa 16-mbit (dd28f032sa 32-mbit) flashfile? memory, this card takes advantage of a revolutionary architecture that provides innovative capabilities, low-power operation and very high read/write performance. the series 2+ card provides todays highest density, highest performance nonvolatile read/write solution for solid-state storage applications. these applications are enhanced further with this products symmetrically- blocked architecture, extended mtbf, low-power 3.3 v operation, built-in v pp generator, and multiple block locking methods. the series 2+ cards dual read and write voltages allow interchange between 3.3 v and 5.0 v systems. series 2+ flash memory cards 4-, 8-, 20- and 40 megabytes imc004flsp, IMC008FLSP, imc020flsp, imc040flsp
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the imc004flsp, IMC008FLSP, imc020flsp, imc040flsp may contain design defects or errors known as errata. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation, 1997 cg-041493 *third-party brands and names are the property of their respective owners.
e series 2+ flash memory cards 3 contents page page 1.0 scope of document.................................5 2.0 product overview ...................................5 3.0 series 2+ architecture overview......6 3.1 card signal description................................6 3.2 series 2+ card control logic .....................10 3.2.1 address decode logic ........................10 3.2.2 data control ........................................10 3.3 component management registers ...........11 3.4 smartpower ...............................................11 4.0 device command set..............................14 5.0 device status register .......................17 6.0 pcmcia card information structure................................................19 7.0 system design considerations ........23 7.1 power supply decoupling ..........................23 7.2 power-up/down protection ........................23 7.3 hot insertion/removal................................23 8.0 electrical specifications..................24 8.1 absolute maximum ratings........................24 8.2 operating conditions..................................24 8.3 capacitance ...............................................24 8.4 dc characteristics .....................................25 8.5 dc characteristics cmos interfacing v cc = 3.3 v ...............................................26 8.6 dc characteristicscmos interfacing v cc = 5.0 v ...............................................27 8.7 dc characteristicsttl interfacing v cc = 3.3 v ...............................................28 8.8 dc characteristicsttl interfacing v cc = 5.0 v ...............................................29 8.9 ac characteristics......................................31 8.9.1 read operations: common memory....31 8.9.2 write operations: common and attribute memory ...............................33 8.9.3 ce#-controlled write operations: common and attribute memory ..........35 8.9.4 power-up/power-down .......................37 8.10 erase and data write perfomance ...........38 9.0 packaging .................................................39 10.0 ordering information........................41 11.0 additional information .....................41
series 2+ flash memory cards e 4 revision history number description -001 original version -002 page buffer write to flash command code correction (from 08h to 0ch) series 2+ tuples and ac characteristics tables include support for 150 ns access -003 ttl dc characteristics tables added general dc characteristics table changed to reflect ttl levels -004 ac characteristics condensed to include v pp pump information 005 series 2+ 8-meg and 40-meg cards added to datasheet component management register tables reformatted i ccr values increased for cmos and ttl 3.3 v timings updated to 250 ns. -006 changed i ppsl and i pps max values -007 changed cmos interfacing dc characteristics to increase v cc sleep current
e series 2+ flash memory cards 5 1.0 scope of document the documentation for intels series 2+ flash memory card includes this datasheet and the series 2+ flash memory card users manual (297373). the datasheet provides all ac and dc characteristics (including timing waveforms) and a convenient reference for the device command set and the cards integrated registers (including the 28f016sas status registers). the series 2+ memory card users manual provides a complete description of the methods for using the card. it also contains the full list of software algorithms and flowcharts and a section for upgrading intels series 2 flash memory cards designs. 2.0 product overview the 4-, 8-, and 20-mbyte series 2+ flash memory cards each contain a flash memory array that consists of two, four, and ten 28f016sa tsop memory devices, respectively. each 28f016sa contains 32 distinct, individually-erasable, 64- kbyte blocks. therefore, the 4-, 8-, and 20-mbyte cards contain 64, 128 and 320 independantly lockable blocks, respectively. the 40-mbyte series 2+ flash memory cards contain a flash memory array that consists of ten dd28f032sa tsop memory devices. each dd28f032sa contains two 28f016sa die in a single package, resulting in 64 distinct, individually-erasable, 64-kbyte blocks. the 40- mbyte cards have 640 independently lockable blocks. the series 2+ card offers additional product features to those of the series 2 card family (refer to the imc0xxflsa datasheets). some of the more notable card-level enhancements include: interchangeable operation at 3.3 v or 5.0 v, block locking and internal v pp generation. the series 2+ card incorporates v cc detect circuitry, referred to as smartpower, to sense the voltage level present at the card interface. the cards control logic automatically configures its circuitry and the 28f016sa/dd28f032sa memory array accordingly. the card information structure (cis) reports that the card is 3.3 v or 5.0 v compatible. the card also detects the presence of 12.0 v on the v pp pin and passes this supply to each memory device. when the 12.0 v power supply is unavailable, the card can generate the required v pp via its internal v pp generation circuitry, whether v cc is 3.3 v or 5.0 v. at the device level, internal algorithm automation allows write and erase operations to be executed using a two-write command sequence in the same way as the 28f008sa flashfile memory in the series 2 card. a super-set of commands and additional performance enhancements have been added to the basic 28f008sa command set: page buffer write to flash results in writes up to four times faster than series 2 cards. command queueing permits the devices to receive new commands during the execution of the current command set. automatic data writes during erase allows the 28f016sa to perform write operations to one block of memory while performing an erase on another block. software locking of memory blocks provides a means to selectively protect code or data within the card. erase all unlocked blocks provides a quick and simple method to sequentially erase all the blocks within a 28f016sa memory device. the series 2+ card has two ways to put the flash devices into a sleep mode for reduced power consumption: 1. issue a command to individual devices, referred to as the software-controlled sleep mode. the device will retain status register data contents and finish any operation in progress using this approach. 2. write to the cards pcmcia-compatible configuration and status register to activate a reset power-down to all devices simultaneously. the card achieves its pcmcia-compatible word- wide access by pairing the 28f016sa/ dd28f032sa devices resulting in an accessible memory block size of 64 kwords. the cards decoding logic (contained within the asics) allows the system to write or r ead one word at a time, or one byte at a time by referencing the high or low byte. erasure can be performed on the entire block pair (high and low byte simultaneously) or on the high and low portions separately. although the 28f016sa/dd28f032sa support byte or word- wide data access, the byte interface was utilized within the card to allow the delivery of higher
series 2+ flash memory cards e 6 performance benefits, such as doubling the effective page buffer size and write performance. the series 2+ cards asics also contain the component management registers that provide five control functions: ready-busy mode selection, software write protection, card status, voltage control, and soft reset. the memory card interface supports the personal computer memory card industry association (pcmcia 2.10) and japanese electronics industry development association (jeida 4.1) 68-pin card format. the series 2+ flash card meets all pcmcia/jeida type 1 mechanical specifications. 3.0 series 2+ architecture overview the series 2+ card consists of three major functional elementsthe flash memory array, card control and smartpower circuitry. the card control logic handles the interface between the flash memory array and the host systems pcmcia signals. smartpower circuitry provides the cards integrated v pp generator and a means for detecting the sockets voltage levels. 3.1 card signal description the 68-pin pcmcia format provides the system interface for the series 2+ flash memory card (see tables 1 and 2). the detailed specifications for this interface is described in the pcmcia 2.10 standard specification . the series 2+ flash card product family conforms to the requirements of previous pcmcia versions release 1.0, release 2.0 and release 2.01 of the pc card standard . release 2.10 redefined pins 43 and 57 as vs 1 and vs 2 (previously refresh and rfu, respectively).
e series 2+ flash memory cards 7 d<15:0> a<25:0> reg# ce # 1 ce # 2 we# oe# rst wait# rdy/bsy# cd # 2 cd # 1 rdy/bsy# wp card control logic zdq<15:8> zdq<7:0> za<20:0> zwe# zoe# zce #<7:0> 0 1 zce #<7:0> zry/zby# zrp# zwp ry/by# rp# wp ce # 0 ce # 1 28f016sa device 8 v cc 3/5# v pp v ss 28f016sa device 6 ry/by# rp# wp ce # 0 ce # 1 28f016sa device 1 v cc 3/5# v pp v ss 28f016sa device 5 v cc 3/5# v pp v ss 28f016sa device 9 v cc 3/5# v pp v ss v cc 3/5# v pp v ss v cc v pp v ss generation circuitry v pp v cc v pp2 v pp1 smartpower v ss v cc 3/5# 28f016sa device 0 v cc 3/5# v pp v ss ry/by# rp# wp ce # 0 ce # 1 d<7:0> a<20:0> we# oe# d<7:0> a<20:0> we# oe# d<7:0> a<20:0> we# oe# d<7:0> a<20:0> we# oe# d<7:0> a<20:0> we# oe# d<7:0> a<20:0> we# oe# ry/by# rp# wp ce # 0 ce # 1 ry/by# rp# wp ce # 1 ce # 0 ry/by# rp# wp ce # 0 ce # 1 vs 1 vs 2 bvd 1 bvd 2 0621_01 figure 1. series 2+ flash memory card block diagram showing major functional elements
series 2+ flash memory cards e 8 table 1. series 2+ flash memory card signals pin signal i/o function active pin signal i/o function active 1 gnd ground 27 a 2 i address bit 2 2dq 3 i/o data bit 3 28 a 1 i address bit 1 3dq 4 i/o data bit 4 29 a 0 i address bit 0 4dq 5 i/o data bit 5 30 dq 0 i/o data bit 0 5dq 6 i/o data bit 6 31 dq 1 i/o data bit 1 6dq 7 i/o data bit 7 32 dq 2 i/o data bit 2 7ce 1 # i card enable 1 low 33 wp o write protect high 8a 10 i address bit 10 34 gnd ground 9 oe# i output enable low 35 gnd ground 10 a 11 i address bit 11 36 cd 1 # o card detect 1 low 11 a 9 i address bit 9 37 dq 11 i/o data bit 11 12 a 8 i address bit 8 38 dq 12 i/o data bit 12 13 a 13 i address bit 13 39 dq 13 i/o data bit 13 14 a 14 i address bit 14 40 dq 14 i/o data bit 14 15 we# i write enable low 41 dq 15 i/o data bit 15 16 rdy/bsy# o ready/busy low 42 ce 2 # i card enable 2 low 17 v cc supply voltage 43 vs 1 o voltage sense 1 low 18 v pp1 supply voltage 44 rfu reserved 19 a 16 i address bit 16 45 rfu reserved 20 a 15 i address bit 15 46 a 17 i address bit 17 21 a 12 i address bit 12 47 a 18 i address bit 18 22 a 7 i address bit 7 48 a 19 i address bit 19 23 a 6 i address bit 6 49 a 20 i address bit 20 24 a 5 i address bit 5 50 a 21 i address bit 21 25 a 4 i address bit 4 51 v cc supply voltage 26 a 3 i address bit 3 52 v pp2 supply voltage
e series 2+ flash memory cards 9 table 1. series 2+ flash memory card signals (continued) pin signal i/o function active pin signal i/o function active 53 a 22 i address bit 22 61 reg# i attribute memory select low 54 a 23 i address bit 23 62 bvd 2 o battery voltage detect 2 55 a 24 i address bit 24 63 bvd 1 o battery voltage detect 1 56 a 25 i address bit 25 64 dq 8 i/o data bit 8 57 vs 2 o voltage sense 2 n.c. 65 dq 9 i/o data bit 9 58 rst i reset high 66 dq 10 i/o data bit 10 59 wait# o extend bus cycle low 67 cd 2 # o card detect 2 low 60 rfu reserved 68 gnd ground table 2. series 2+ flash memory card signal description symbol type name and function a 0 Ca 25 input address inputs: address a 0 through a 25 are address bus lines which enable direct addressing of up to 64 megabytes of memory on the card. signal a 0 is not used in word access mode. a 25 is the most significant bit. dq 0 Cdq 15 input/ output data input/output: dq 0 through dq 15 constitute the bi-directional data bus. dq 15 is the most significant bit. ce 1 #,ce 2 # input card enable 1 & 2: ce 1 # enables even bytes, ce 2 # enables odd bytes. multiplexing a 0 , ce 1 # and ce 2 # allows 8-bit hosts to access all data on d 0 through d 7 . oe# input output enable: active low signal gating read data from the memory card. we# input write enable: active low signal gating write data to the memory card. rdy/bsy# output ready/busy output: indicates status of internally timed erase or write activities. a high output indicates the memory card is ready to accept accesses. a low output indicates that a device in the memory card is busy with internally timed erase or write activities. cd 1 #,cd 2 # output card detect 1 & 2: these signals provide for correct memory card insertion detection. they are positioned at opposite ends of the card to detect proper alignment. the signals are connected to ground internally on the memory card, and will be forced low whenever a card is placed in the socket. the host socket interface circuitry shall supply 10k or larger pull-up resistors on these signal pins. wp output write protect: write protect reflects the status of the write protect switch on the memory card. wp set to high = write protected, providing internal hardware write lockout to the flash array.
series 2+ flash memory cards e 10 table 2. series 2+ flash memory card signal description (continued) symbol type name and function v pp1 ,v pp2 write/erase power supply: (12 v nominal) for erasing memory array blocks or writing bytes in the array. these pins must be 12 v to perform and write/erase operation when not using the cards integrated v pp generator. these signals may be disconnected but are required for exca? standard compliance. v cc card power supply: (3.3 v or 5 v nominal) for all internal circuitry. gnd ground for all internal circuitry. reg# input register select: provides access to series 2+ flash memory card registers and card information structure in the attribute memory plane. rst input reset: active high signal for placing card in power-on default state. wait# output wait: (extend bus cycle) this signal is driven high for compatibility. bvd 1 , bvd 2 output battery voltage detect: these signals are driven high to maintain sram card compatibility. vs 1 , vs 2 output voltage sense: notify the host socket of the cards v cc requirements. vs 1 grounded and vs 2 open indicates a 3.3 v/5 v card has been inserted. rfu reserved for future use n.c. no internal connection to card ; pin may be driven or left floating. 3.2 series 2+ card control logic the card control logic, contained within two asics, handles the address decoding and data control for the series 2+ card. the component management registers are also contained within the card control logic. 3.2.1 address decode logic at the highest level, the address decode section determines when to select the common memory (reg# = v ih ) or attribute memory (reg# = v il ) planes. within the attribute memory plane (figure 2) , the address decode logic determines when to select the card information structure (cis) or component management registers (cmr). the cis contains tuple information and is located at even-byte addresses beginning with address 0000h (refer to section 6.0). the cmrs are mapped at even byte locations beginning at address 4000h (refer to section 3.3 for a detailed description). 3.2.2 data control as shown in table 3, data paths and directions are selected by the data control logic using reg#, a 0 , we#, oe#, ce 1 #, and ce 2 # as logic inputs. the data control logic selects any of the pcmcia word- wide, byte-wide, and odd-byte modes for either reads or writes to common or attribute memory. all accesses to the attribute memory plane must be made through d[7:0] no valid data can be written on the high byte. reads of d[15:8] will yield ffh. odd byte even byte not used not used not used memory address 1fffffh 004200h 004000h 000100h 000000h not used component management registers hardwired pcmcia cis 0491_2 figure 2. attribute memory plane
e series 2+ flash memory cards 11 table 3. data access mode truth table common memory plane mode reg# ce 2 #ce 1 #a 0 oe# we# v pp2 v pp1 d[15:8] d[7:0] standby x v ih v ih xxxv ppl v ppl high-z high-z byte-read v ih v ih v il v il v il v ih v ppl v ppl high-z even v ih v ih v il v ih v il v ih v ppl v ppl high-z odd word-read v ih v il v il xv il v ih v ppl v ppl odd even odd byte-read v ih v il v ih xv il v ih v ppl v ppl odd high-z byte-write v ih v ih v il v il v ih v il xxx v pph xxx even v ih v ih v il v ih v ih v il v pph xxx xxx odd word-write v ih v il v il xv ih v il v pph v pph odd even odd byte-write v ih v il v ih xv ih v il v pph v ppl odd xxx attribute memory plane mode reg# ce 2 #ce 1 #a 0 oe# we# v pp2 v pp1 d [15:8] d [7:0] standby x v ih v ih xxxv ppl v ppl high-z high-z byte-read v il v ih v il v il v il v ih v ppl v ppl high-z even v il v ih v il v ih v il v ih v ppl v ppl high-z ffh word-read v il v il v il xv il v ih v ppl v ppl ffh even odd byte-read v il v il v ih xv il v ih v ppl v ppl ffh high-z byte-write v il v ih v il v il v ih v il v ppl v ppl xxx even v il v ih v il v ih v ih v il v ppl v ppl xxx xxx word-write v il v il v il xv ih v il v ppl v ppl xxx even odd byte-write v il v il v ih xv ih v il v ppl v ppl xxx xxx note: when using the v pp generator, v pp1 and v pp2 are dont care. 3.3 component management registers the component management registers (cmrs) are classified into two categories: those defined by pcmcia rev 2.0, and those included by intel to enhance the interface between the host system and the cards flash memory array. the cmrs provide five control functions: ready-musy mode selection, voltage control, software write protection, card status and soft reset. for more details about the cmr functionality, consult intels series 2+ flash memory card users manual (297373). 3.4 smartpower the smartpower circuitry generates and monitors the cards programming voltages. when a host system does not provide a valid v pp supply, the cards integrated generator can be switched on via the voltage control register. the smartpower circuitry also detects the host systems v cc level (3.3 v or 5.0 v) and configures the cards flash memory devices, accordingly driving the 3/5# pin to the memory array to the appropriate value. the smartpower circuitry is enabled by writing a 1 to bit 0 of the voltage control register.
series 2+ flash memory cards e 12 table 4. configuration option register - pcmcia (soft reset register) attribute memory plane address: 4000h read/write sreset levlreq configuration index 76543210 default: 02h bit 7 = soft reset 1 = reset state 0 = end reset cycle bit 6 = level request driven low bits 5-0 = configuration index may be written with values 1-4, refer to index in cis card configuration table tuple. table 5. card configuration and status register - pcmcia (global power-down register) attribute memory plane address: 4002h read/write reserved pwrdwn reserved 76543210 default: 00h bit 2 = power-down 1 = 28f016sas in reset power-down 0 = power-up table 6. card status register - intel attribute memory plane address: 4100h read only reserved sreset cmwp pwrdwn ciswp wp rdy/bsy# 76543210 default: 01h or 03h bit 5 = soft reset 1 = reset state bit 4 = common memory write protect 1 = write protected bit 3 = power-down 1 = power-down bit 2 = common memory cis write protect 1 = write protected bit 1 = write protect switch 1 = write protected bit 0 = card ready/busy# 1 = ready
e series 2+ flash memory cards 13 table 7. write protection register - intel attribute memory plane address: 4104h read/write reserved blken cmwp ciswp 76543210 default: 04h bit 2 = block locking enable 1 = enable independent 28f016sa block locking 0 = all blocks unlocked bit 1 = common memory write protect 1 = common memory minus the cmcis in write protect status 0 = write protect according to independent 28f016sa block locking bit 0 = common memory cis write protect 1 = common memory cis in write protect status 0 = write protect according to independent 28f016sa block locking table 8. voltage control register - intel attribute memory plane address: 410ch read/write v cc level reserved v pp valid v pp gen 76543210 default: 82 or 02h bit 7 = v cc level: read only bit 1 = host supplying 3.3 v 0 = host supplying 5 v bit 1 = v pp valid 1 = v pp between 11.4 v and 12 v 0 = v pp invalid bit 0 = v pp generation 1 = turn on integrated v pp generator 0 = turn off integrated v pp generator note: the v pp valid bit only reflects the state of the v pp generator, not the external v pp . table 9. ready/busy mode register - intel attribute memory plane address: 4140h read/write reserved rack mode 76543210 default: 00h bit 1 = ready acknowledge 0 = clear rdy/bsy# bit 0 = rdy/bsy# mode 1 = high-performance mode 0 = pcmcia level mode
series 2+ flash memory cards e 14 4.0 device command set the 28f016sa/dd28f032sa-based series 2+ command set increases functionality over earlier 28f008sa-based designs while maintaining backwards compatibility. the extended command set incorporates many new features to improve programmability and write performance such as: page buffered writing, individual block locking, multiple rdy/bsy# configurations and device level queuing capabilities. the following pages list the series 2+ command set and bus cycle operations overview. series 2+ command set codes (h) series 2 compatible mode 00h invalid/reserved 10h alternate data write 20h single block erase 40h data write 50h clear status registers 70h read csr 90h read id codes b0h erase suspend d0h confirm/resume ffh read flash array codes (h) series 2+ performance enhancement 0ch page buffer write to flash 71h read gsr or bsrs 72h page buffer swap 74h single load to page buffer 75h read page buffer 77h lock block 80h abort 96h,01h ry/by# level mode enable 96h,02h ry/by# pulse-on-write 96h,03h ry/by# pulse-on erase 96h,04h ry/by# disable 97h upload status bits 99h upload device information a7h erase all unlocked blocks e0h sequential load to page buffer f0h sleep
e series 2+ flash memory cards 15 table 10. 28f008sa-compatible mode command bus definitions first bus cycle second bus cycle command r/w addr data r/w addr data byte word byte word read array w da ffh ffffh r da ad ad intelligent identifier w da 90h 9090h r ia id id read csr (see 1) w da 70h 7070h r da csrd csrd clear status register (see 2) w da 50h 5050h word/byte write w wa 40h 4040h w wa wd wd word/byte write (alternate) w wa 10h 1010h w wa wd wd block erase/confirm w ba 20h 2020h w ba d0h d0d0h erase suspend/resume w da b0h b0b0h w da d0h d0d0h addresses: data: da device address ad array data ba block address csrd csr data ia identifier address id identifier data wa write address wd write data = queueable commands notes: 1. the csr is automatically available after the device enters data write, erase or suspend operations. 2. clears csr.3, csr.4 and csr.5. also clears gsr.5 and all bsr.5 and bsr.2 bits.
series 2+ flash memory cards e 16 table 11. 28f016sa-super-set mode performance enhancement command bus definitions first bus cycle second bus cycle third bus cycle command notes oper addr data oper addr data oper addr data byte word byte word byte word read page buffer w da 75h 7575h r pa pd pdpd page buffer swap 6 w da 72h 7272h single load to page buffer w da 74h 7474h w pa pd pdpd sequential load to page buffer 4,5 w da e0h e0e0h w da bch w da bch page buffer write to flash array 3,4,5 w da 0ch 0c0ch w a 0 bc(l,h) w wa bc(h,l) ry/by# pulse- on-erase 7 w da 96h 9696h w da d0h d0d0h ry/by# pulse- on-write 7 w da 96h 9696h w da d1h d1d1h ry/by# enable to level-mode 7 w da 96h 9696h w da d2h d2d2h ry/by# disable 7 w da 96h 9696h w da d3h d3d3h lock block/ confirm w da 77h 7777h w ba d0h d0d0h upload status bits/ confirm 2 w da 97h 9797h w da d0h d0d0h read extended status registers 1 w da 71h 7171h r ra gsrd/bsrd erase all unlocked blocks/ confirm w da a7h a7a7h w da d0h d0d0h sleep w da f0h f0f0h abort w da 80h 8080h upload device information w da 99h 9999h w da d0h d0d0h
e series 2+ flash memory cards 17 addresses data data counts da device address ad write address wc(l,h) word count (low, high) ba block address csrd csr data bc(l,h) byte count (low, high) ia identifier address g/bsrd gsr/bsr data wd(l,h)v write data (low, high) pa page buffer address id identifier data ra extended register address wd write data wa write address pd page buffer data x dont care = queueable commands notes: 1. ra can be the gsr address or any bsr address. 2. upon device power-up, all bsr lock-bits are locked. the lock status upload command must be written to reflect the actual lock-bit status. 3. a 0 is automatically complemented to load the second byte of data. 4. bch/wch must be at 00h for this product because of the 256-byte page buffer size and to avoid writing the page buffer contents into more than one 256-byte segment within an array block. they are simply shown for page buffer expandability. 5. pa and pd (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle (not shown). 6. this command allows the user to swap between available page buffers (0 or 1). 7. these commands reconfigure ry/by# output to one of two pulse modes, or they enable and disable the r y/by# function. 5.0 device status register each 28f016sa has three types of status registers: the compatible status register (csr), the global status register (gsr) and the block status register (bsr). the csr is identical to the 28f008sa status register. the gsr contains queue and page buffer information about each device. each block within the device has a bsr assigned to it. the bsr contains the block locking status and other information specific to the block being addressed. table 12. compatible status register read only register wsms ess es dws vpps reserved 76543210 default: 80h csr.7 = write state machine status (wsms) 1 = ready 0 = busy csr.6 = erase-suspend status (ess) 1 = erase suspended 0 = erase in progress/completed csr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase csr.4 = data-write status (dws) 1 = error in data write 0 = data write successful csr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok
series 2+ flash memory cards e 18 table 13. global status register wsms oss dos dss qs pbas pbs pbss 76543210 notes: gsr.7 = write state machine status 1 = ready 0 = busy [1] ry/by# output or wsms bit must be checked to determine completion of an operation (block lock, erase suspend, any ry/by# reconfig- uration, upload status bits, block erase or data program) before the appropriate status bit (oss or dos) is checked for success. gsr.6 = operation suspend status 1 = operation suspended 0 = operation in progress/completed gsr.5 = device operation status 1 = operation unsuccessful 0 = operation successful or currently running gsr.4 = device sleep status 1 = device in sleep 0 = device not in sleep matrix 5/4 0 0 = operation successful or currently running 0 1 = device in sleep mode or pending sleep 1 0 = operation unsuccessful 1 1 = operation unsuccessful or aborted if operation currently running, then gsr.7 = 0. if device pending sleep, then gsr.7 = 0. operation aborted: unsuccessful due to abort command. gsr.3 = queue status 1 = queue full 0 = queue available gsr.2 = page buffer available status 1 = one or two page buffers available 0 = no page buffer available the device contains two page buffers. gsr.1 = page buffer status 1 = selected page buffer ready 0 = selected page buffer busy selected page buffer is currently busy with wsm operation. gsr.0 = page buffer select status 1 = page buffer 1 selected 0 = page buffer 0 selected note: 1. when multiple operations are queued, checking bsr.7 only provides indication of completion for that particular block. gsr.7 provides indication when all queued operations are completed.
e series 2+ flash memory cards 19 table 14. block status register bs bls bos boas qs vpps reserved 76543210 default: 80h bsr.7 = block status (bs) 1 = ready 0 = busy bsr.6 = block-lock status (bls) 1 = block unlocked for write/erase 0 = block locked for write/erase bsr.5 = block operation status (bos) 1 = operation unsuccessful 0 = operation successful or currently running bsr.4 = block operation abort status (boas) 1 = operation aborted 0 = operation not aborted bsr.3 = queue status (qs) 1 = queue full 0 = queue available bsr.2 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok 6.0 pcmcia card information structure the card information structure (cis) begins at address 00000000h of the cards attribute memory plane. it contains a variable length chain of data blocks (tuples) that conform to a basic format (table 15). the cis of the series 2+ flash memory card is found in table 16. table 15. pcmcia tuple format bytes data 0 tuple code: cistpl_xxx. the tuple code 0ffh indicates no more tuples in the list. 1 tuple link: tpl_link. link to the next tuple in the list. this can be viewed as the number of additional bytes in tuple, excluding this byte. a link field of zero indicates an empty tuple body. a link field containing 0ffh indicates the last tuple in the list. 2-n bytes specific to this tuple.
series 2+ flash memory cards e 20 table 16. tuples for series 2+ card address value description address value description 00h 01h cistpl_device 3ah a0h 28f016 j-id 02h 04h tpl_link 3ch 00h null control tuple 04h 57h flash 3eh 15h cistpl vers 1 06h 22h 150 ns 40h 39h tpl_link 32h 250 ns 42h 04h tpllv1_major card size 44h 01h tpllv1_minor 08h 0eh 4 mb tpllv1_info 1eh 8 mb 46h 49h i 4eh 20 mb 48h 6eh n 9eh 40 mb 4ah 74h t 0ah ffh end of device 4ch 65h e 0ch 1ch cistpl_device_oc 4eh 6ch l 0eh 05h tpl_link 50h 00h end text 10h 02h other conditions - 3 v cc 52h 53h s 12h 57h flash 54h 32h 2 14h 32h 250 ns 56h 45h e card size 58h 34h 4 mb 16h 0eh 4 mb 38h 8 mb 1eh 8 mb 32h 20 mb 4eh 20 mb 34h 40 mb 9eh 40 mb 5ah 20h 4 mb 18h ffh end of device 20h 8 mb 1ah 17h cistpl_device_a 30h 20 mb 1ch 04h tpl_link 30h 40 mb 1eh 1fh rom 5ch 53h s 20h 22h 150 ns 20h space 22h 01h 2 kb 5eh 57h w 24h ffh end of device 20h space 26h 1dh cistpl_device_oa 60h 00h endtext 28h 05h tpl_link 62h 43h c 2ah 02h other conditions - 3 v cc 64h 4fh o 2ch 17h rom 66h 50h p 2eh 32h 250 ns 68h 59h y 30h 01h 2 kb 6ah 52h r 32h ffh end of device 6ch 49h i 34h 18h cistpl jedec_c 6eh 47h g 36h 02h tpl_link 70h 48h h 38h 89h intel j-id 72h 54h t
e series 2+ flash memory cards 21 table 16. tuples for series 2+ card (continued) address value description address value description 74h 20h space beh 40h tpcc_radr 76h 49h i c0h 03h tpcc_rmsk 78h 6eh n c2h 00h null control tuple 7ah 74h t c4h 1bh cistpl_cftable_entry 7ch 65h e c6h 08h tpl_link 7eh 6ch l c8h 01h tpce_index (01h) 80h 20h space cah 01h tpce_fs ( v cc only) 82h 43h c tpce_pd 84h 4fh o cch 79h v cc parameter 86h 52h r selection byte 88h 50h p ceh 55h v cc nominal voltage 8ah 4fh o 5 v 5% 8ch 52h r d0h 53h i cc static 500 a 8eh 41h a d2h 1eh i cc average 150 ma 90h 54h t d4h 1eh i cc peak 150 ma 92h 49h i d6h 1bh i cc pwrdwn 200 a 94h 4fh o d8h 1bh cistpl_cftable_entry 96h 4eh n dah 0fh tpl_link 98h 20h space dch 02h tpce_index (02h) 9ah 31h 1 deh 02h tpce_fs (v cc and v pp ) 9ch 39h 9 tpce_pd 9eh 39h 9 e0h 79h v cc parameter a0h 33h 3 selection byte a2h 20h space e2h 55h v cc nominal voltage a4h 47h g 5 v 5% a6h 4ch l e4h 2bh i cc static 250 a a8h 41h a e6h 06h i cc average 100 ma aah 44h d e8h 06h i cc peak 100 ma ach 45h e eah 52h i cc pwrdwn 50 a aeh 4bh k tpce_pd b0h 00h end text ech 79h v pp parameter b2h ffh end of list selection byte b4h 1ah cistpl_conf eeh 8eh 12.0 v 5% b6h 05h tupl_link f0h 7dh nc ok on standby & pwd b8h 01h tpcc_sz f2h 53h i pp static 500 a bah 04h tpcc_last f4h 25h i pp average 20 ma bch 00h tpcc_radr f6h 25h i pp peak 20 ma
series 2+ flash memory cards e 22 table 16. tuples for series 2+ card (continued) address value description address value description f8h 52h i pp pwrdwn 50 a 136h 00h null control tuple fah 1bh cistpl_cftable_entry 138h 1eh cistpl devicegeo fch 09h tpl_link 13ah 06h tpl_link feh 03h tpce_index (03h) 13ch 02h dgtpl_bus 100h 01h tpce_fs (v cc only) 13eh 11h dgtpl_ebs tpce_pd 140h 01h dgtpl_rbs 102h 79h v cc parameter 142h 01h dgtpl_wbs selection byte 144h 01h dgtpl_part = 1 104h b5h v cc = 3.3 v 146h 01h flash device 106h 1eh extension byte interleave 108h 04h i cc static 1 ma 148h 20h cistpl_manfid 10ah 1eh i cc average 150 ma 14ah 04h tpl_link (04h) 10ch 1eh i cc peak 150 ma tplmid_manf 10eh 53h i cc pwrdwn 500 a 14ch 89h lsb 110h 1bh cistpl_cftable_entry 14eh 00h msb 112h 10h tpl_link 150h 12h 4 mb - 150 ns 114h 04h tpce_index (04h) 22h 8 mb - 150 ns 116h 02h tpce_fs (v cc and v pp ) 42h 20 mb - 150 ns tpce_pd 62h 40 mb - 150 ns 118h 79h v cc parameter 152h 84h tplmid_card msb selection byte 154h 21h cistpl_funcid 11ah b5h v cc = 3.3 v 156h 02h tpl_link 11ch 1eh extension byte 158h 01h tplfid_function 11eh 2bh i cc static 250 a (memory) 120h 06h i cc average 100 ma 15ah 00h tplfid_sysinit (none) 122h 06h i cc peak 100 ma 15ch ffh cistpl_end 124h 52h i cc pwrdwn 50 a 00h invalid address tpce_pd (156h-1feh) 126h 79h v pp parameter selection byte 128h 8eh 12.0 v =/- 5% 12ah 7dh nc ok on standby & pwd 12ch 53h i pp static 500 a 12eh 25h i pp average 20 ma 130h 25h i pp peak 20 ma 132h 1bh i pp pwrdwn 150 a 134h 00h null control tuple
e series 2+ flash memory cards 23 7.0 system design considerations 7.1 power supply decoupling flash memory power-switching characteristics require careful device decoupling. system designers are interested in three supply current issues: standby, active and transient current peaks which are produced by rising and falling edges of ce 1 # and ce 2 #. the capacitive and inductive loads on the card and internal flash memory device pairs determine the magnitudes of these peaks. three-line control and proper decoupling capacitor selection suppress transient voltage peaks. series 2+ cards contain on-card ceramic decoupling capacitors connected between v cc and gnd, and between v pp1 /v pp2 and gnd. the card connector should also have a 4.7 f electrolytic capacitor between v cc and gnd, as well as between v pp1 /v pp2 and gnd. the bulk capacitors overcome voltage slumps caused by printed-circuit-board trace inductance, and supply charge to the smaller capacitors as needed. 7.2 power-up/down protection the pcmcia/jeida-specified socket properly sequences the power supplies to the flash memory card via shorter and longer pins. this design assures that hot insertion and removal will not result in card damage or data loss. each device in the memory card is designed to offer protection against accidental erasure or writing, caused by spurious system-level si gnals that may exist during power transitions. the card will power-up into the read state. a system desi gner must guard against active writes for v cc voltages above v lko when v pp is active. since both we# and ce 1 # must be low for a command write, driving either to v ih will inhibit writes. with its control register architecture, alteration of device contents only occurs after successful completion of the two-step command sequences. while these precautions are sufficient for most applications, an alternative approach would allow v cc to reach its steady state value before raising v pp1 /v pp2 above v cc + 2.0 v. in addition, upon powering down, v pp1 /v pp2 should be below v cc + 2.0 v before lowering v cc . note the integrated v pp generator defaults to the power off condition after reset and system power-up. the v pp generation circuitry must be enabled for the memory card to operate in 3.3 v-only or 5.0 v-only mode. 7.3 hot insertion/removal the capability to remove or insert pc cards while the system is powered on (i.e., hot insertion/removal) requires careful design approaches on the system and card levels. to design for this capability, consider card over- voltage stress, system power fluxuations and control line stability.
series 2+ flash memory cards e 24 8.0 electrical specifications 8.1 absolute maximum ratings* operating temperature during read ........................... 0 c to +60 c (1) during write .............................. 0 c to +60 c storage temperature................ C30 c to +70 c (2) voltage on any pin with respect to ground ...... C2.0 v to v cc +2.0 v (2) v pp1 /v pp2 supply voltage with respect to ground .. C2.0 v to v cc +14.0 v (2,3) v cc supply voltage with respect to ground .................C0.5 v to +7.0 v notice: this is a production datasheet. the specifications are subject to change without notice. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. operating temperature is for commercial product defined by this specification. 2. minimum dc input voltage is -0.5 v. during transitions, inputs may undershoot to 2.0 v for periods less than 20 ns. maximum dc voltage on output pins is v cc +0.5 v, which may overshoot to v cc + 2.0 v for periods less than 20 ns. 3. maximum dc input voltage on v pp1 /v pp2 may overshoot to +14.0 v for periods less than 20 ns. 4. v pp generator turned on for 3.3 v or 5.0 v only operation. 8.2 operating conditions temperature and v cc operating conditions symbol parameter min max units v cc at 3.3 v, 12 v v pp v cc supply voltage ( 0.3 v) 3.0 3.6 v v cc at 3.3 v, v pp gen (4) v cc supply voltage ( 0.1 5 v ) 3.15 3.45 v v cc at 5. 0 v v cc supply voltage ( 0.2 5 v ) 4.75 5.25 v 8.3 capacitance (1) t a = +25 c, f = 1 mhz symbol pins typ max unit c in a 0 15 30 pf c in address/control 10 20 pf c in v cc , v pp 22pf c out output 10 20 pf
e series 2+ flash memory cards 25 8.4 dc characteristics symbol parameter notes min max units test conditions i li input leakage current 1,3 20 m av cc = v cc max v in = v cc or gnd i lo output leakage current 1 20 m av cc = v cc max v out =v cc or gnd v il5 input low voltage 1 0 0.8 v v cc = 5 v v il3.3 0.7 v cc = 3.3 v v ih5 input high voltage 1 2.4 v cc + 0.5 v v cc = 5 v v ih3.3 2.2 v cc + 0.3 v cc = 3.3 v v ol output low voltage 1 0.4 v i ol = 3.2 ma v oh output high voltage 1 v cc C 0.4 v cc vi oh = C2.0 ma v ppl v pp during read only operations 1,2 0 6.5 v v pph v pp during read/write operations 1 11.4 12.6 v v lko v cc erase/write lock voltage 1 2.0 v notes: 1. values are the same for byte and word wide modes for all card densities. 2. block erases/data writes are inhibited when v pp and v ppl are not guaranteed in the range between v pph and v ppl . 3. exceptions: with v in = gnd, the leakage current on ce 1 #, ce 2 #, reg#, oe#, and we# will be < 500 m a due to internal pull-up resistors. with v in = v cc , rst leakage current will be < 500 m a due to internal pull- down resistors. with v in = v cc , a 21 Ca 25 leakage current will be <100 a due to internal pull down resistors.
series 2+ flash memory cards e 26 8.5 dc characteristics cmos interfacing v cc = 3.3 v sym parameter density notes x8 mode x16 mode unit test conditions (mbytes) typ max typ max i ccr v cc read current 4, 8, 20, 40 1, 2, 3 75 100 ma v cc = v cc max t cycle = 250 ns i ccw v cc write current 4, 8, 20, 40 1, 2, 3, 4 40 50 ma v pp gen = off during data write 1, 2, 3, 5 100 175 ma v pp gen = on during data write i cce v cc erase current 4, 8, 20, 40 1, 2, 3, 4 40 50 ma v pp gen = off 1, 2, 3, 5 80 150 ma v pp gen = on i ccsl v cc sleep current 4 1, 3, 4, 6 25 75 25 75 m av cc = v cc max 8 25 95 25 95 control signals = 20 35 155 35 155 v cc 40 45 255 45 255 i ccs v cc standby 4 1, 2, 3, 75 115 110 210 m av cc = v cc max current 8 4, 6 80 125 115 230 control signals = 20 85 155 120 250 v cc 40 100 200 150 300 i ppw v pp write current 4, 8, 20, 40 1, 2, 3, 4 10 15 20 30 ma data write in progress v pp = v pph i ppe v pp erase current 4, 8, 20, 40 1, 2, 3, 4 6 12 12 22 ma block (pair) erase in progress v pp = v pph i ppsl v pp sleep current 4, 8, 20, 40 1, 2, 3, 4 0 0.5 0 0.5 ma v pp v cc i pps v pp standby/ read current 4, 8, 20, 40 1, 2, 3, 4 0 0.5 0 0.5 ma v pp v cc cmos test conditions: v il = gnd 0.2 v v ih = v cc 0.2 v notes: 1. all currents are rms values unless otherwise specified. typical v cc = 5 v , v pp = 12 v, t = 25 c. 2. two devices active in word mode, one device active in byte mode. 3. devices not addressed are in sleep mode. 4. v pp generation circuitry turned off. 5. v pp generation circuitry turned on. 6. control signals, ce 1 #, ce 2 #, oe#, we#, reg#.
e series 2+ flash memory cards 27 8.6 dc characteristics cmos interfacing v cc = 5.0 v sym parameter density notes x8 mode x16 mode unit test conditions (mbytes) typ max typ max i ccr v cc read current 4, 8, 20, 40 1, 2, 3 140 160 ma v cc = v cc max t cycle = 250 ns i ccw v cc write current 4, 8, 20, 40 1, 2, 3, 4 85 120 ma v pp gen = off during data write 1, 2, 3, 5 120 150 ma v pp gen = on during data write i cce v cc erase current 4, 8, 20, 40 1, 2, 3, 4 75 100 ma v pp gen = off 1, 2, 3, 5 100 75 150 ma v pp gen = on i ccsl v cc sleep current 4 1, 3, 4, 6 25 75 25 75 m av cc = v cc max 8 25 95 25 95 control signals = 20 35 155 35 155 v cc 40 45 255 45 255 i ccs v cc standby 4 1, 2, 3, 75 115 110 210 m av cc = v cc max current 8 4, 6 80 125 115 230 control signals = 20 85 155 120 250 v cc 40 100 200 150 300 i ppw v pp write current 4, 8, 20, 40 1, 2, 3, 4 6 12 14 24 ma data write in progress v pp = v pph i ppe v pp erase current 4, 8, 20, 40 1, 2, 3, 4 6 12 12 22 ma block (pair) erase in progress v pp = v pph i ppsl v pp sleep current 4, 8, 20, 40 1, 2, 3, 4 0 0.5 0 0.5 ma v pp v cc i pps v pp standby/ read current 4, 8, 20, 40 1, 2, 3, 4 0 0.5 0 0.5 ma v pp v cc cmos test conditions: v il = gnd 0.2 v, v ih = v cc 0.2 v notes: 1. all currents are rms values unless otherwise specified. typical v cc = 5 v, v pp = 12 v, t = 25 c. 2. two devices active in word mode, one device active in byte mode. 3. devices not addressed are in sleep mode. 4. v pp generation circuitry turned off. 5. v pp generation circuitry turned on. 6. control signals, ce 1 #, ce 2 #, oe#, we#, reg#.
series 2+ flash memory cards e 28 8.7 dc characteristics ttl interfacing v cc = 3.3 v sym parameter density notes x8 mode x16 mode unit test conditions (mbytes) typ max typ max i ccr v cc read current 4, 8, 20, 40 1, 2, 3 75 90 ma v cc = v cc max t cycle = 250 ns i ccw v cc write current 4, 8, 20, 40 1, 2, 3, 4 85 100 ma v pp gen = off during data write 1, 2, 3, 5 150 225 ma v pp gen = on during data write i cce v cc erase current 4, 8, 20, 40 1, 2, 3, 4 85 100 ma v pp gen = off 1, 2, 3, 5 125 180 ma v pp gen = on i ccsl v cc sleep current 4, 8, 20, 40 1, 3, 4, 6 70 70 ma v cc = v cc max control signals = v ih i ccs v cc standby current 4, 8, 20, 40 1, 2, 3, 4, 6 70 70 ma v cc = v cc max control signals = v ih i ppw v pp write current 4, 8, 20, 40 1, 2, 3, 4 10 15 20 30 ma data write in progress v pp = v pph i ppe v pp erase current 4, 8, 20, 40 1, 2, 3, 4 5 10 10 20 ma block (pair) erase in progress v pp = v pph i ppsl v pp sleep current 4, 8, 20, 40 1, 2, 3, 4 0 0.5 0 0.5 ma v pp v cc i pps v pp standby/ read current 4, 8, 20, 40 1, 2, 3, 4 0 0.5 0 0.5 ma v pp v cc ttl test conditions: v il = 0.7 v, v ih = 2.2 v notes: 1. all currents are rms values unless otherwise specified. typical v cc = 5 v , v pp = 12 v, t = 25 c. 2. two devices active in word mode, one device active in byte mode. 3. devices not addressed are in sleep mode. 4. v pp generation circuitry turned off. 5. v pp generation circuitry turned on. 6. control signals, ce 1 #, ce 2 #, oe#, we#, reg#.
e series 2+ flash memory cards 29 8.8 dc characteristics ttl interfacing v cc = 5.0 v sym parameter density notes x8 mode x16 mode unit test conditions (mbytes) typ max typ max i ccr v cc read current 4, 8, 20, 40 1, 2, 3 170 190 ma v cc = v cc max t cycle = 150 ns i ccw v cc write current 4, 8, 20, 40 1, 2, 3, 4 135 170 ma v pp gen = off during data write 1, 2, 3, 5 170 250 ma v pp gen = on during data write i cce v cc erase current 4, 8, 20, 40 1, 2, 3, 4 125 150 ma v pp gen = off 1, 2, 3, 5 150 200 ma v pp gen = on i ccsl v cc sleep current 4, 8, 20, 40 1, 3, 4, 6 100 100 ma v cc = v cc max control signals = v ih i ccs v cc standby current 4, 8, 20, 40 1, 2, 3, 4, 6 100 100 ma v cc = v cc max control signals = v ih i ppw v pp write current 4, 8, 20, 40 1, 2, 3, 4 7 12 14 24 ma data write in progress v pp = v pph i ppe v pp erase current 4, 8, 20, 40 1, 2, 3, 4 5 10 10 20 ma block (pair) erase in progress v pp = v pph i ppsl v pp sleep current 4, 8, 20, 40 1, 2, 3, 4 0 0.5 0 0.5 ma v pp v cc i pps v pp standby/ read current 4, 8, 20, 40 1, 2, 3, 4 0 0.5 0 0.5 ma v pp v cc ttl test conditions: v il = 0.8 v, v ih = 2.4 v notes: 1. all currents are rms values unless otherwise specified. typical v cc = 5 v , v pp = 12 v, t = 25 c. 2. two devices active in word mode, one device active in byte mode. 3. devices not addressed are in sleep mode. 4. v pp generation circuitry turned off. 5. v pp generation circuitry turned on. 6. control signals, ce 1 #, ce 2 #, oe#, we#, reg#.
series 2+ flash memory cards e 30 test points input output 1.5 0.7 v 0.4 1.5 cc 0491_07 figure 3. transient input/output reference waveform (v cc = 5.0 v) for standard test configuration test points input output 1.5 3.0 0.0 1.5 0491_08 figure 4. transient input/output reference waveform (v cc = 3.3 v) for standard test configuration
e series 2+ flash memory cards 31 8.9 ac characteristics ac timing diagrams and characteristics are designed to meet or exceed pcmcia 2.1 specifications. no delay occurs when switching between the common and attribute memory planes. 8.9.1 read operations: common memory symbol parameter 150 ns at 5 v 250 ns at 3.3 v unit jedec pcmcia min max min max t avav t rc read cycle time 150 250 ns t avqv t a (a) address access time 150 250 ns t elqv t a (ce) card enable access time 150 250 ns t glqv t a (oe) output enable access time 75 125 ns t ehqx t dis (ce) output disable time from ce# 75 100 ns t ghqz t dis (oe) output disable time from oe# 75 100 ns t glqx t en (ce) output enable time from ce# 5 5 ns t elqx t en (oe) output enable time from oe# 5 5 ns t phqv power-down recovery to output delay. v cc = 5 v 530 670 ns note: 1. sampled, not 100% tested
series 2+ flash memory cards e 32 049102 figure 5. ac waveforms for read operations
e series 2+ flash memory cards 33 8.9.2 write operations: common and attribute memory (1) symbol parameter 150 ns at 5 v 250 ns at 3.3 v unit jedec pcmcia min max min max t avav t c w write cycle time 150 250 ns t wlwh t w (we) write pulse width 80 150 ns t avwl t su (a) address setup time 20 30 ns t avwh t su (a-weh) address setup time for we# 100 180 ns t vpwh t vps v pp setup to we# going high 100 180 ns t elwh t su (ceweh) card enable setup time for we# 100 180 ns t dvwh t su (d-weh) data setup time for we# 50 80 ns t whdx t h (d) data hold time 20 30 ns t whax t rec (we) write recover time 20 30 ns t whrl we# high to rdy/bsy# 140 140 ns t qvvl v pp hold from operation complete 00ns t whgl t h (oe-we) output enable hold from we# 80 120 ns t phwl power-down recovery to we# going low 11 s note: 1. read timing characteristics during erase and data write operations are the same as during read-only operations. refer to read operations: common memory
series 2+ flash memory cards e 34 addresses (a) ce# (e) oe# (g) we# (w) data (d/q) rp# ih v il v ih v il v ih v il v ih v il v il v in d in a in a valid srd in d whrl t high z whdx t ih v il v v (v) pp 12 3 4 6 5 pph v ih v ppl v avav t avwh t whax t dvwh t wlwh t qvvl t vpwh t in d avwl t whgl t whqv1,2 t elwh t phwl t rdy/bsy# (r) il v ih v oh v ol v 0491_04 notes: 1. v cc power-up and standby 2. write program or erase setup command 3. write valid address and program or erase confirm command 4. automated program or erase delay 5. read status register data 6. write read array command figure 6. ac waveforms for write operations
e series 2+ flash memory cards 35 8.9.3 ce#-controlled write operations: common and attribute memory symbol parameter 150 ns at 5 v 250 ns at 3.3 v unit jedec pcmcia min max min max t avav t c w write cycle time 150 250 ns t eleh t w (we) chip enable pulse width 80 150 ns t avel t su (a) address setup time 20 30 ns t aveh t su (a-weh) address setup time for ce# 100 180 ns t vpeh t vps v pp setup to ce# going high 100 180 ns t wleh t su (ce-weh) write enable setup time for ce# 100 180 ns t dveh t su (d-weh) data setup time for ce# 50 60 ns t ehdx t h (d) data hold time 20 30 ns t ehax t rec (we) write recover time 20 30 ns t ehrl ce# high to rdy/bsy# 140 140 ns t qvvl v pp hold from operation complete 00ns t ehgl t h (oe-we) output enable hold from we# 80 120 ns t phel power-down recovery to ce# going low 11 s note: 1. read timing characteristics during erase and data write operations are the same as during read-only operations. refer to read operations: common memory .
series 2+ flash memory cards e 36 addresses (a) we# (w) oe# (g) ce# (e) data (d/q) rp# ih v il v ih v il v ih v il v ih v il v il v in d in a in a valid srd in d ehrl t high z ehdx t ih v il v v (v) pp 12 3 4 6 5 pph v ih v ppl v avav t aveh t ehax t dveh t eleh t qvvl t vpeh t in d avel t ehgl t ehqv1,2 t wleh t phel t rdy/bsy# (r) il v ih v oh v ol v 0491_05 notes: 1. v cc power-up and standby 2. write data write or erase setup command 3. write valid address and data (data write) or erase confirm command 4. automated data write or erase delay 5. read status register data 6. write read array command figure 7. alternate ac waveform for write operations
e series 2+ flash memory cards 37 8.9.4 power-up/power-down symbol parameter notes min max units pcmcia v i (ce) ce# signal level (0.0 v < v cc < 2.0 v) 1 0 v imax v ce# signal level (2.0 v < v cc < v ih )1v cc - 0.1 v imax v ce# signal level (v ih < v cc )1v ih v imax v t su (v cc ) ce# setup time 20 ms t su (reset) ce# setup time 20 ms t rec (v cc ) ce# recover time 1.0 s t pr v cc rising time 2 0.1 300 ms t pf v cc falling time 2 3.0 300 ms t w (reset) reset width 10 s t h (hi-z reset) reset width 1 ms t s (hi-z reset) reset width 0 ms notes: 1. v imax means absolute maximum voltage for input in the period of 0.0 v < v cc < 2.0 v, v i (ce#) is only 0.00 v ~ v imax . 2. the t pr and t pf are defined as linear waveforms in the period of 10% to 90%, or vice-versa. even if the waveform is not a linear waveform, its rising and falling time must meet this specification. 049105 figure 8. power-up timing for systems supporting reset#
series 2+ flash memory cards e 38 8.10 erase and data write perfomance (1,3) v cc = 3.3 v 0.3 v, t a = 0 c to +70 c sym parameter notes min typ (1) max units test conditions page buffer word write time 2 2.2 s t whqv1 t ehqv1 word/byte write time 2 9 s 3 ms t whqv2 t ehqv2 block write time 2 0.6 2.1 sec byte write mode block erase time 2 0.8 10 sec full chip erase time 2 51.2 sec v cc = 5.0 v 0. 5 v , t a = 0 c to +70 c sym parameter notes min typ (1) max units test conditions page buffer word write time 2 2.1 s t whqv1 t ehqv1 word byte/write time 2,4 6 s 3 ms t whqv2 t ehqv2 block write time 2 0.4 2.1 sec byte write mode block erase time 2 0.6 10 sec full chip erase time 2 38.4 sec notes: 1. 25 c, and normal voltages. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. to maximize system performance, the rdy/bsy# signal should be polled instead of using the maximum word/byte write time as a delay timer. the maximum word/byte write time is the absolute maximum time it takes the write algorithm to complete. the overwhelming majority of the bits program in the typical value specified.
e series 2+ flash memory cards 39 9.0 packaging 049106.eps
series 2+ flash memory cards e 40 049107.eps
e series 2+ flash memory cards 41 10.0 ordering information imc020flsp,sbxxxxx where: i = intel mc = memory card 020 = density in megabytes (004,020 available) fl = flash technology s = blocked architecture p = performance sbxxxxx = customer identifier 11.0 additional information order number document 290434 series 2 flash memory cards datasheet 297373 series 2+ flash memory card user's manual 290489 28f016sa 16-mbit (1 mb x 16, 2 mb x 8 ) flashfile? memory datasheet 290429 28f008sa 8-mbit (1 mb x 8) flashfile? memory datasheet 292126 ap-377 the 28f016sa software drivers note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers sho uld contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

▲Up To Search▲

Price & Availability of IMC008FLSP

	To Download IMC008FLSP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .